1. Field of the invention:
The present invention relates to a method and device for testing analog and mixed-signal circuits.
In the present disclosure and in the appended claims, the term "mixed signal circuit" is intended to designate a circuit including both analog and digital circuitry.
2. Brief description of the prior art:
Due to the development of integrating technologies and the market requirements, the trend of designing mixed-signal ASICs (Application-Specific Integrated Circuits) has significantly increased. Analog testing is a challenging task and is considered as one of the most important problems in analog and mixed-signal ASIC design. The specifications of analog circuits are usually very large which results in long testing time and poor fault coverage. A dedicated test equipment is also required. Furthermore, it is very difficult to establish universal fault models equivalent to the so called stuck-at models in digital circuits.
A fault can be either catastrophic or parametric. Catastrophic faults result in complete absence of the desired function. On the other hand, parametric faults result in functional circuit but with degraded performance. Catastrophic faults are easier to test, but when the complexity of the CUT (Circuit Under Test) increases they cause many problems. Parametric faults are the most important and hard to test faults. It should be pointed out that most of the existing test methods address only the catastrophic faults.
Known methods for testing analog blocks comprise functional (or parametric) testing, DC (Direct Current) testing, and power supply current (I.sub.DDQ) monitoring. Functional (or parametric) testing has been described in the following four articles:
[1] C.-L Wey, "Built-In Self-Test Structure for Analog Circuit Fault Diagnosis", IEEE Transactions on Instrumentation and Measurement, 39(3), 1990, pp. 517-521. PA0 [2] L. Milor et al., "Optimal Test Set Design for Analog Circuits", IEEE ICCAD, 1990, pp. 294-297. PA0 [3] P. P. Fasang, D. Mulins and T. Wong, "Design for Testability for Mixed Analog/Digital ASICs", IEEE Custom Integrated Circuit Conf., 1988, pp. 16.5.1-16.5.4. PA0 [4] K. D. Wagner and T. W. Williams, "Design for Testability of Mixed signal Integrated Circuits", IEEE Int. Test Conf., 1988, pp. 823-829. PA0 [5] M. J. Marlett and J. A. Abraham, "DC IATP-An Iterative Analog Circuit Test Generation Program for Generating Single Pattern Tests", IEEE Int. Test Conf., 1988, pp. 839-844. PA0 [6] G. Devarayanadurg and M. Soma, "Analytical Fault Modelling and Static Test Generation for Analog ICs", IEEE ICCAD, 1994, pp. 44-47. PA0 [7] G. Gielen, Z. Wang and W. Sansen, "Fault Detection and Input Stimulus Determination for the Testing of Analog Integrated Circuits Based on Power-Supply Current Monitoring", IEEE ICCAD, 1994, pp. 495-498. PA0 [8] P. Nigh and W. Maly, "Test Generation for Current Testing", IEEE Design & Test of Computers, Vol. 7, No. 2, 1990, pp. 26-38.
DC testing has been suggested in the following two articles:
Power-supply current (I.sub.DDQ) monitoring is discussed in the following two publications:
Various designs for testability (DFT) rules have been used in conjunction with the above mentioned test methods to ease the test problem (articles [3] and [4]). These techniques are employed during the design stage to increase the controllability and observability and to facilitate the test task. Some of these techniques for digital testing have been the subject of U.S. Pat. No. 4,513,418 (P. H. Bardell et al.) issued on Apr. 23, 1985 for an invention entitled "Simultaneous Self Testing System" and U.S. Pat. No. 4,749,947 granted to T. R. Gheewala on Jun. 7, 1988 for an invention entitled "Cross-Check Test Structure for Testing Integrated Circuits".
The effectiveness of the above methods depends strongly on the selection of suitable test vectors. Also, they need a large number of test vectors to validly testing the functionality of the CUT. When the complexity of the CUT increases, the problem of determining optimal test vectors becomes critical. Furthermore, the process of choosing a suitable form of excitation signals and evaluation of the results is time consuming. BIST (Built-In Self-Test) strategies based of above methods require the use of specialized input stimuli generation and output evaluation hardware which introduce significant area overhead.